FIG. 1 illustrates a prior art variable gain amplifier (VGA). The amplifier 10 shown in FIG. 1 includes a first differential pair of transistors Q1,Q2 biased by a first tail current 2ID, and a second differential pair of transistors Q3,Q4 biased by a second tail current 2IN. The bases of Q1 and Q4 are connected, and the bases of Q2 and Q3 are connected. The collectors of Q1 and Q2 are coupled to the connected bases through a loop amplifier 12, which may be nothing more than a pair of emitter followers.
The operation of this basic translinear VGA was analyzed in an article by Barrie Gilbert, “A New Wide-band Amplifier Technique”, IEEE J. Solid-State Circuits, vol. SC-3, no. 4, pp. 353-365 (December 1968). Assuming that the transistors are matched, the common base connections between the inner and outer transistors and the common emitter connections within the pairs force the current ratio between Q1 and Q2 to equal the current ratio between Q3 and Q4. A differential current applied to Q1 and Q2 at nodes A and B can be defined in terms of a modulation factor x that varies between −1 and +1. Thus, the currents through Q1 and Q2 are shown as (1+x)ID and (1−x)ID, respectively. The modulation factor x is replicated at the second differential pair, and thus, the currents through Q3 and Q4 are shown as (1−x)IN and (1+x)IN, respectively. When no differential current is applied to Q1 and Q2 (i.e., x=0), a current ID passes through each of Q1 and Q2, and a current IN passes through each of Q3 and Q4. When a non-zero differential current is applied to Q1 and Q2 (x≠0), the currents through Q3 and Q4 are modulated by the same factor x. The current gain of this cell is simply the ratio of the tail currents, i.e., IN/ID.
The amplifier 10 of FIG. 1 can be configured as an input VGA (IVGA) by providing for control of the input tail current ID. In this configuration it is useful, e.g., for conditioning an input signal with a wide dynamic range (such as a received RF signal) before presenting that signal to circuitry that expects signals in a fairly constant range (e.g., automatic gain control applications). Amplifier 10 can also be configured as an output VGA (OVGA) by providing for control of the output tail current. In this configuration it is useful, e.g., for variable output power/drive applications. Also, since the output current varies linearly with changes in the output tail current, an appropriately designed OVGA can be used as a multiplier. U.S. Pat. Nos. 6,894,564 and 7,190,227, which have a common inventor with this disclosure and are incorporated by reference, disclose some improvements in which the gain of the loop amplifier is coordinated with the gain of the input pair to provide constant bandwidth operation.
FIG. 2 illustrates a prior art variable gain amplifier (VGA) based on a continuously interpolated attenuator. The circuit of FIG. 2 includes an attenuator network 14, a series of transconductance (gm) stages implemented as differential pairs QA1,QB1 . . . QAN,QBN, and a main amplifier 16. The attenuator receives an input signal VIN and generates a series of progressively attenuated signals at output tap points TP1 . . . TPN. Each gm stage is coupled to one of the tap points to receive one of the attenuated signals. The output currents from the gm stages are summed at nodes N1 and N2 and provided to the main amplifier so that the overall output signal is determined by the sum of the output signals from all of the gm stages.
The gm stages are biased by interpolator signals I1 . . . IN from an interpolator (not shown). The interpolator generates the signals I1 . . . IN as a series of continuous, overlapping Gaussian-shaped current pulses having a centroid whose location moves along the series of gm stages as the gain is varied so that most of the interpolator signals are nearly zero, but adjacent stages near the centroid are enabled to some extent.
At the highest gain setting, essentially all of the current from the interpolator is steered to the gm stage closest to the input end of the attenuator (QA1,QB1). Therefore, the first gm stage is active, and the remaining gm stages are effectively off. As the gain is reduced, the interpolator steers the bias current to gm stages further away from the input end of the attenuator, thereby selecting gm stages that receive progressively attenuated versions of the input signal.
As the gain is swept from one extreme to the other, the gm stages are sequentially enabled and disabled in a continuous manner in which one of the interpolation signals gradually increases while the adjacent interpolation signal gradually decreases. Thus, as the gain changes, a centroid or point of action can be envisioned as moving along the series of gm stages to provide continuous interpolation between the tap points. For any given gain setting (in general, other than an extreme minimum or maximum) multiple gm stages are enabled to varying degrees so that the transmission of signals from different attenuator tap points is altered smoothly and continuously. Many improvements to the circuit of FIG. 2 are disclosed in numerous U.S. patents including U.S. Pat. Nos. 6,525,601 and 5,684,431 which have a common inventor with this disclosure.
The VGA illustrated in FIG. 1 is generally configured as an IVGA to cope with varying input signals. A prior art continuously interpolated VGA that is generally configured as an OVGA to provide an output signal of varying amplitude is disclosed in U.S. Patent Application Publication No. 2005/0030121 which has a common inventor with this patent disclosure and is incorporated by reference.
Although the variable-gain amplifiers discussed above provide outstanding performance in many signal processing applications, the presence of analog variable-gain elements in the signal path may introduce noise, nonlinearities, and other problems that limit the performance of the amplifier. For example, in the circuit of FIG. 1, the differential pairs Q1,Q2 and Q3,Q4 operate as analog variable-gain elements and may introduce noise that reduces the dynamic range. They may also introduce nonlinearities that cause distortion.
In the circuit of FIG. 2, the gm stages QA1,QB1 . . . QAN,QBN also operate as analog variable-gain elements, and therefore, may introduce noise and distortion. Moreover, because of their overlapping operation, they may introduce another type of inaccuracy that may be referred to as partition noise, or multiplied noise. That is, in the circuit of FIG. 2, the input signal VIN is attenuated and then partitioned between adjacent gm stages. The amount of signal that is steered by adjacent stages, however, may not be precise because of noise or variations in the interpolator signals and/or gain control signal. The uncertainty or vacillation between the amount of signal steered by adjacent stages may cause low frequency noise to show up in the frequency spectrum of the output signal that does not exist in the input signal. In a VGA having a single analog variable-gain element, the bias noise is common mode and gets cancelled at the output. However, in a VGA having multiple overlapping analog variable-gain elements, this noise is uncorrelated and thus shows up in the output spectrum. Also, since the analog variable-gain elements essentially behave like multipliers, they tend to convert and move noise from point-to-point in the frequency spectrum.
Some of the problems associated with analog variable-gain elements may be overcome by utilizing amplifiers having multiple switched signal paths to provide discrete gain settings in response to a digital word. These amplifiers are known as digitally controlled variable-gain amplifiers (DGAs) and programmable gain amplifiers (PGAs). DGAs and PGAs typically utilize arrays of switches to switch different amounts of attenuation and/or gain into and out of the signal path. To provide small enough gain steps, numerous switches must be controlled by a suitably large digital word. If the word is applied to the amplifier in a parallel format, it increases the number of terminals which drives up the cost of the amplifier. To reduce the required number of terminals, the digital word may be input through a serial interface, but this increases the amount of support logic required to decode the serial data.